The present invention relates to a varactor, and in particular, a varactor for radio frequency transceivers.
As known, varactors are electronic devices having a variable capacity, selectable in particular through a biasing voltage, applied between a pair of terminals.
Varactors are used, for example, for tuning LC circuit radio-frequency transceivers. In fact, these circuits are adversely affected by production inaccuracies, and by the low quality factor of the passive components, and thus, in use, require adaptation of the actual reactance value, to adjust it to the planned values.
For this purpose a POS (Polysilicon-Oxide-Semiconductor) varactor has been recently proposed, described for example in the article xe2x80x9cA xc2x130% Tuning Range Varactor Compatible with future Scaled Technologiesxe2x80x9d, by R. Castello, P. Erratico, S. Manzini, F. Svelto, VLSI Symp. on Circuits, Dig. Techn. Papers, June 1998, pp. 34-35, and illustrated in FIG. 1. In detail, a varactor 1 is formed in a wafer 2, only partially shown for easy of representation, comprising a substrate 3, of P-type, having a surface 8 and accommodating a well 4 of Nxe2x88x92 type. In turn, the well 4 accommodates two biasing regions 5a and 5b, of N+ type, spaced from one another (but electrically connected, as shown in FIG. 1, by an electrical connection 20) and bias the well 4 to voltage VN.
A gate region 6, made of polycrystalline silicon, extends above surface 8 of wafer 2, at an intermediate wafer portion 7 between biasing regions 5a and 5b, and is electrically isolated from the wafer portion 7 by a gate oxide region 9. The gate region 6 is biased to a voltage VG, via an electrical connection line 21.
As apparent to those skilled in the art, the conductivity of the wafer portion 7 depends on the voltage difference VVAR=VGxe2x88x92VN existing between gate region 6 and well 4. In particular, when the gate region 6 is biased to a positive voltage VG, charges (electrons) are accumulated in the wafer portion 7 and the capacity of the varactor 1 increases to a value CMAX, beyond which it remains constant, and can no longer be modulated. This capacity value CMAX, equivalent to the capacity of gate oxide layer 9, is reached for values of VVAR slightly higher than 0 V (for example 0.3 V-0.4 V). If, on the other hand, voltage VVAR is negative, a depletion region 10 is formed in the wafer portion 7, the depth whereof increases along with the absolute value of inverse voltage VVAR, thus causing the capacity of the varactor 1 to decrease down to a minimum value CMIN, when the inverse voltage VVAR reaches a negative threshold value VT (for example of approximately xe2x88x921.6 V). In fact, below the threshold value VT, in the wafer portion 7, next to the surface 8 of the wafer 2, an inversion layer 11 is formed, comprising minority carriers (here gaps), thermally generated in the depletion region 10. The wafer portion 7 thus defines a capacity modulation region. For example, in a typical MOS process, CMAX is approximately equivalent to 500 nF/cm2, and CMIN is approximately equivalent to 250 nF/cm2.
However, the present production technology for integrated transceivers requires more extensive variability.
An embodiment of the present invention provides a varactor, the capacity of which can be modified within a wider range than those obtained at present.
According to the present invention, an embodiment of a varactor is provided, as defined in the claims.